Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM
نویسندگان
چکیده
This paper presents a methodology and techniques for automated integration of dedicated hardwired (HW) IP cores into heterogeneous multiprocessor systems. We propose an IP core integration approach based on an HW module generation that consists of a wrapper around a predefined IP core. This approach has been implemented in a tool called ESPAM for automated multiprocessor system design, programming, and implementation. In order to keep high performance of the integrated IP cores, the structure of the IP core wrapper is devised in a way that adequately represents and efficiently implements the main characteristics of the formal model of computation, namely, Kahn process networks, we use as an underlying programming model in ESPAM. We present details about the structure of the HW module, the supported types of IP cores, and the minimum interfaces these IP cores have to provide in order to allow automated integration in heterogeneous multiprocessor systems generated by ESPAM. The ESPAM design flow, the multiprocessor platforms we consider, and the underlying programming (KPN) model are introduced as well. Furthermore, we present the efficiency of our approach by applying our methodology and ESPAM tool to automatically generate, implement, and program heterogeneous multiprocessor systems that integrate dedicated IP cores and execute real-life applications.
منابع مشابه
Ultraperformance Wireless Interconnect Nanonetworks for Heterogeneous Gigascale Multi-Processor SoCs
To bridge the widening gap between computation requirements and communication efficiency faced by gigascale heterogeneous multi-processor SoCs in the upcoming billiontransistor era, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), is proposed by using the recently developed RF interconnection. With the uniqueness of wireless interconnection, the WNoC design paradigm c...
متن کاملA System-Level Solution for Dependable Heterogeneous MPSoCs
Mission-critical systems require a dependable operation during their lifetime. However, the current ongoing aggressive scaling of technology has resulted in increasing reliability issues. Dependability of such systems has become a major concern in the design process. In this work we aim to enhance the dependability of heterogeneous Multi-Processor System-on-Chips (MPSoCs) by introducing a syste...
متن کاملNetwork-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication requirements of MPSoCs made of hundreds of cores will not be feasible using a single shared bus or a hierarchy of buses due to their poor sca...
متن کاملAnalog IP Filter Cores With Embedded Test For Design Reuse
Current technology allows for the integration of complete systems onto a single chip. These systems on chip (SoC) are increasingly designed by connecting together large pre-designed and verified modules, called cores, with the advantage being a faster design cycle. The development of third party Intellectual Property (IP) cores is a rapidly expanding industry, and whereas initially these were n...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- EURASIP J. Emb. Sys.
دوره 2008 شماره
صفحات -
تاریخ انتشار 2008